Cadence Design Systems unveiled its third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, and switch fabric systems on chip (SoCs) The innovative architecture offers 25% power savings, 40% area reduction and better design margins over the second-generation architecture. The 1-112G gapless data rate support provides excellent I/O flexibility for chip-to-chip connectivity for AI/ML accelerator SoCs.
Source: https://www.helpnetsecurity.com/2021/05/26/cadence-112g-lr-serdes-ip/